1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various novel methods of forming trench/hole type features in a layer of material of an integrated circuit product.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET (whether an NFET or a PFET) is a device that typically includes a source region, a drain region, a channel region that separates the source region and the drain region, and a gate electrode positioned above the channel region. A gate insulation layer is positioned between the gate electrode and the channel region that will be formed in the substrate. Electrical contacts are made to the source and drain regions, and current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. Traditionally, FETs have been substantially planar devices, but similar principles of operation apply to more three-dimensional FET structures, devices that are typically referred to as FinFETs.
A typical integrated circuit product also includes many levels, e.g., 7-10, of so-called metallization layers that constitute the electrical “wiring” that provides a means to electrically connect to the integrated circuits formed in the semiconducting substrate. The metallization layers comprise layers of insulating materials having various conductive structures, e.g., conductive lines and vias, formed therein. Typically, the conductive vias provide electrical connection between an underlying conductive line in an underlying metallization layer and an overlying conductive line in an overlying metallization layer. In current-day, high performance integrated circuit products, the conductive lines and vias are typically formed using single-damascene or dual-damascene techniques, although such conductive structures may sometimes be formed using traditional deposition/photolithography/patterning techniques. Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” or ULK dielectric materials (for example, materials having a dielectric constant less than 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using aluminum for the conductive lines and vias. The use of low-k dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants.
As noted above, in modern ultra-high density integrated circuits, device features have been steadily decreased in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. However, such reductions in the size of the device features, and the associated increase in packing density, mandates that other aspects of the integrated circuit product must also be reduced in size. This means that, among other things, the various conductive lines and vias in the metallization layers of an integrated circuit product must be compressed into ever-decreasing plot space and that the physical size of the conductive lines and vias must also be reduced. In turn, this increased overall “crowding” of the various conductive lines and vias means that device designers have had to become very creative in terms of minimizing the physical size of such conductive lines and vias and in providing means to insure proper alignment between adjacent levels of such conductive structures when alignment tolerances or “process windows” are very small.
In many cases, formation of a conductive line or via in a layer of insulating material involves forming a trench-type or hole-type feature, respectively, in a layer of insulating material. At a high level, the process of forming a conductive line/via generally involves depositing a layer of insulating material, forming a patterned etch mask comprised of a photoresist material above the layer of insulating material, performing an etching process through the etch mask to define the trench/hole type feature in the layer of insulating material, removing the patterned etch mask, overfilling the trench/hole type feature with a conductive material, such as copper, and removing excess portions of the conductive material positioned outside of the trench/hole type feature by performing a chemical mechanical planarization (CMP) process. Such processes are well known to those skilled in the art.
By way of background, photolithography tools and systems typically include a source of radiation at a desired wavelength, an optical system and, typically, the use of a so-called mask or reticle that contains a pattern that is desired to be formed on a wafer. Radiation is provided through or reflected off the mask or reticle to form an image on a light-sensitive layer of photoresist material that is formed above a semiconductor wafer. The radiation used in such systems may be light, such as ultraviolet light, deep ultraviolet light (DUV), vacuum ultraviolet light (VUV), extreme ultraviolet light (EUV), etc. The radiation may also be x-ray radiation, e-beam radiation, etc. Ultimately, after so-called photoresist development, a patterned photoresist mask layer is formed that may be used for a variety of purposes, e.g., as an etch mask to form trench/hole type features in an underlying layer of insulating material. Currently, most of the photolithography systems employed in semiconductor manufacturing operations are so-called deep ultraviolet systems (DUV) that generate radiation at a wavelength of 248 nm or 193 nm. However, the capabilities and limits of traditional DUV photolithography systems are being tested as device dimensions continue to shrink. A typical photolithography process generally involves the steps of: (1) applying a layer of photoresist above a wafer or substrate, typically accomplished by a spin-coating process; (2) pre-baking (or soft-baking) the layer of photoresist at a temperature of approximately 90-120° C. to reduce the level of solvents in the layer of photoresist and to improve the adhesion characteristics of the photoresist; (3) performing an exposure process, wherein a pattern on a reticle is projected onto the layer of photoresist used in a stepper tool to create a latent image in the layer of photoresist; (4) performing a post-exposure bake on the layer of photoresist at a temperature approximately 5-15° C. higher than the pre-bake process; (5) performing a develop process to turn the latent image in the layer of photoresist into the final resist image; and (6) performing a post-bake process (or hard-bake) at a temperature of approximately 125-160° C. to remove residual solids and to improve adhesion of the patterned photoresist mask. These process steps result in a “post-litho” patterned etch mask. The above processes are well known to those skilled in the art and, thus, will not be described herein in any greater detail.
As it relates to actually forming a trench/hole type feature in a layer of insulating material, the trench/hole type feature has a target critical dimension (CD) or width that the process engineer tries to achieve based on the design criteria and rules for the particular product under design. Historically, when trench/hole type features were larger in size, they were formed in a layer of insulating material by forming a post-litho etch mask that had openings that corresponded to the trench/hole type features that were to be directly etched into the underlying layer of insulating material. This was typically accomplished by using a dark-tone reticle (a “dark-field” mask) with a clear-field opening (that corresponds to the trench/hole type feature) to expose the layer of photoresist and using a so-called positive tone developer (PTD) that removed the exposed photoresist material. Thereafter, a positive etch bias etch process was performed to define the trench/hole type feature in the underlying layer of material, wherein the feature exhibited substantially vertical sidewalls. A positive etch bias etch process is one whereby the etched feature has a larger dimension than that of the corresponding feature defined in the patterned layer of photoresist. For example, a square opening in a patterned layer of photoresist may have a critical dimension of 40 nm. When a positive etch bias etch process is performed through the photoresist mask to form, for example, a contact opening in an underlying layer of material, the contact opening will have a larger critical dimension, e.g., 50 nm, than that of the opening in the patterned layer of photoresist.
However, as dimensions continued to shrink, the aforementioned PTD/positive etch bias etch process technique proved to be inadequate to produce the very small conductive lines and vias required on modern integrated circuit products. Thus, the industry evolved to using a so-called negative tone developer (NTD) process coupled with a negative etch bias etching process to produce the required smaller features. In general, this process involves forming a patterned layer of photoresist where the post-litho openings are as close as possible to the final desired target dimension for the feature. This required pushing the photolithography equipment to its limits to produce a patterned layer of photoresist with such very small sized post-litho openings. The NTD process involved use of a clear-tone reticle (a “clear-field” mask) with a dark-field line that corresponds to the trench/hole type feature to expose the layer of photoresist. Using an NTD, the exposed photoresist material is left in place while the non-exposed material is removed. Thereafter, a negative etch bias etch process was performed to define the trench/hole type feature in the underlying layer of material, wherein the feature exhibited inwardly tapered sidewalls. A negative etch bias etch process is one whereby the etched feature has a smaller dimension than that of the corresponding feature defined in the patterned layer of photoresist. For example, a square opening in a patterned layer of photoresist may have a critical dimension of 40 nm. When a negative etch bias etch process is performed through the photoresist mask to form, for example, a contact opening in an underlying layer of material, the contact opening will have a smaller critical dimension, e.g., 30 nm, than that of the opening in the patterned layer of photoresist. Simply put, the negative etch bias process was performed as a means to effectively reduce the critical dimension of the resulting conductive line/via beyond what could be directly patterned using the previous PTD/positive etch bias processing techniques described above.
FIG. 1 depicts a prior art formation process for two illustrative trench/hole type features 10A/10B and will be referenced to further explain some of the problems associated with existing prior art methodologies. FIG. 1 depicts the features at three points during the fabrication process: (1) as-drawn target during the design process; (2) the post-lithography condition after a patterned photoresist mask has been formed based upon the as-drawn target; and (3) the post-etch condition. The upper portion of FIG. 1 depicts the tip-to-tip spacing between the features, whereas the lower portion of FIG. 1 depicts the tip-to-side spacing between the features. As indicated in FIG. 1, the dimensions of the feature changes during the course of the lithography and etching processes and the spacing between the features changes accordingly.
As shown in FIG. 1, the features have a target length 12T, a post-litho length 12PL and a post-etch length 12PE, wherein the post-litho length 12PL is greater than the target length 12T, and the post-etch length 12PE is less than the target length 12T. Similarly, the features have a target width 14T, and a post-litho width 14PL that is greater than the target width 14T. In the depicted example, the post-etch width 14PE is equal to the target width 14T. The target dimensions of the features are drawn as precisely as the photolithography systems and materials will allow. However, as indicated in FIG. 1, the overall size of the feature, post-lithography, tends to be larger than its target dimensions, e.g., the post-lithography length 12PL and width 14PL are larger than the target length 12T and target width 14T, respectively. This is due to the limitations of traditional deep UV photolithography systems as it relates to trying to directly image smaller and smaller features. Additionally, as reflected in FIG. 1, due to so-called etch-bias, the post-etch feature tends to be smaller in physical size than the post-litho feature, i.e., the post-etch length 12PE and width 14PE are less than post-litho length 12PL and width 14PL, respectively.
The reduction in size of the features from the post-litho size to the post-etch size enables the desired reduction in feature size in terms of the width or critical dimension of the trench/hole type features which is necessary in manufacturing modern integrated circuit products. However, the magnitude of dimensional changes in the features is different in the length direction as compared to the width direction of the feature. More specifically, there is a length or tip etch bias 18 and a width or side etch bias 20. With continuing reference to FIG. 1, the tip-to-tip spacing for the target condition 16T, the post-litho condition 16PL and the post-etch condition 16PE are depicted. In general, as it relates to tip-to-tip spacing, the post-litho spacing 16PL is less than the target spacing 16T and the post-etch spacing 16PE is even less than the target spacing 16T. Similarly, post-litho width 14PL is greater than the target width 14T or the post-etch width 14PE. By way of example only, the post-litho spacing 16PL may be 50 nm, while the post-etch spacing 16PE may be 80 nm which equates to a tip etch bias 18 of 15 nm. Similarly, post-litho width 14PL may be about 40 nm, while the post-etch width 14PE may be about 20 nm, which equates to a side etch bias 20 of 10 nm. This overall change in the feature size from post-lithography to post-etch is sometimes referred to as “line-end-pull-back,” which is typically described by a ratio between the tip etch bias 18 and the side etch bias 20. In the example described above, the line-end-pull-back would be about 1.5 (15/10). Similarly, the post-etch tip-to-side spacing 15PE is greater than the post-litho tip-to-side spacing 17PL due to this line-end-pull-back issue.
Importantly, as noted above, the tip etch bias 18 is greater than the side etch bias 20, which can have adverse effects on tip-to-tip and tip-to-side spacing between features because of the increased loss in the length direction when forming trench/hole type features as described above. FIG. 2 depicts situations wherein the above-described difference in etch bias may have adverse impacts as it relates to forming conductive lines and vias on integrated circuit products. FIG. 2 depicts three situations (“short,” “target” and “open”) for the connection between where conductive line features 30A, 30B are formed in a first layer of insulating material and a conductive line feature 32 formed in an overlying layer of insulating material. Ideally, in the target situation, the tip-to-tip spacing 30S between the conductive line features 30A, 30B will be large enough such that the overlying conductive line 32 will only be conductively coupled to the feature 30A and it will not be conductively coupled to the feature 30B. If the tip-to-tip spacing between the features 30A, 30B becomes smaller than the target spacing 30S, then a short circuit will occur as the features 30A, 30B will contact one another, as indicated at the arrow 34, and the line 32 is conductively coupled to the feature 30B. Conversely, if the tip-to-tip spacing becomes wider than the target spacing 30S, an open circuit will result as the line 32 is not conductively coupled to the feature 30A. Negative etch biasing also has the undesirable effect of creating trench/hole type features with inwardly sloped sidewalls, i.e., the width at the top of the trench/hole type feature is greater than width at the bottom of the trench/hole type feature. The key metric for tip-to-tip spacing for trench/hole type features is the critical dimension at the bottom of the opening (because it is the bottom of the feature that makes contact with an underlying feature in an underlying metallization layer), which becomes larger post-etch than it is post-litho. Thus, while use of negative etch bias etching processes can produce features having very small critical dimensions, e.g., very narrow metal lines, the reduction in feature size can undesirably increase spacing between adjacent structures, e.g., it can increase tip-to-tip and tip-to-side spacing, which may lead to some of the problems identified above. Ideally, the cross-sectional configuration of the trench/hole type feature would be approximately rectangular or square with substantially vertically oriented sidewalls.
The present disclosure is directed to various novel methods of forming trench/hole type features in a layer of material of an integrated circuit product that may solve or reduce one or more of the problems identified above.